The so-called intelligent power switches are finding widespread industrial application. These devices can drive any kind of load (capacitive, inductive and/or resistive), referred to ground (in a high-side driver configuration) or to the power supply voltage (in a low-side driver configuration). They are called "intelligent" because on a single chip are integrated circuits capable of protecting and regulating in a real time mode the state of the integrated power switch (for example to protect the integrated power device from a short circuit etc).
At present, the most used technology for fabricating these integrated circuits is the so-called mixed or BCD technology (Bipolar-CMOS-DMOS). The integrated switch is often realized by a DMOS transistor, which, as compared with a bipolar transistor of similar current handling capacities, has the advantages of being voltage-driven, is capable of withstanding the maximum process voltage and has a lower saturation resistance.
On the other hand, in the field of industrial applications, the problem of electromagnetic disturbances that may be produced by continuous fast switchings of relays and equipment is very important. In order to minimize the electromagnetic noise that is produced, it is important to realize switches that are capable of ensuring suitably slow slew rates, in practice switching fronts having a controlled slope.
A common approach for switching-on and off a power transistor (power switch) with controlled switching fronts is that of loading and discharging the driving node of the transistor (the gate in the case of a field effect power transistor) with a constant current. Such a driving scheme, in case of a high-side driver employing a field effect power transistor (FET) is depicted in FIG. 1.
As well known to a skilled technician, such a solution does not permit perfectly controlled slew rates to be obtained because the slope of the switching front depends on the capacitance of the gate node; and this capacitance is not constant but assumes different values as the transistor passes from an off condition to a saturation condition and from the latter to a so-called linear working condition (i.e. an operating zone of its characteristic where the FET exhibits a resistive behaviour). Moreover, such a solution normally requires a circuitry capable of speeding up the passage from an off condition to a saturation condition at the beginning of a rising front and conversely at the end of the descending front, and also for speeding up the passing from a saturation condition to a linear operating condition at the end of a rising front and viceversa at the beginning of a descending front, in order to maintain the turn-on and turn-off delays acceptably small.
An alternative approach used for controlling the slew rate is based upon the use of a high gain operational amplifier, configured as an integrating stage, employing a capacitor C in its feedback line, as shown in FIG. 2.
Compared to the first solution, this alternative solution provides perfectly controlled switching fronts, because they are exclusively defined by the ratios between I.sub.ON /C and I.sub.OFF /C.
On the other hand, the operational amplifier must be provided with an output stage capable of driving the gate of the power FET (for example a DMOS transistor) which may have a parasitic capacitance of a value that may be as low as ten odd pF and as large as several thousands pF and a broad band width in order to prevent oscillations.
Even though this last approach may theoretically achieve a perfect slew rate control by suitably dimensioning the current generators I.sub.OFF and I.sub.ON and the bootstrap capacitance C (which may also be connected externally of the integrated circuit and therefore adapted according to need), it has the drawback of being unable to optimize also power consumption and the switching delays.
For these reasons, this solution is seldom employed in systems and equipment where power consumption of the control circuitry and operation at a relatively high switching frequency are important considerations.
Moreover, in case of a power MOSFET, the driving must commonly be effected with a boosted voltage for reducing the resistance Ron of the power transistor. Therefore it is important that the current draw from the supply node of the final stage of the driving operational amplifier, which is adequately boosted by employing a charge pump circuit, be as slow as possible to avoid overloading the charge pump circuit.